Advanced verification techniques : a systemC based approach by Leena Singh

By Leena Singh

"As chip measurement and complexity keeps to develop exponentially, the demanding situations of practical verification have gotten a serious factor within the electronics undefined. it truly is now typically heard that logical blunders overlooked in the course of useful verification are the most typical reason behind chip re-spins, and that the prices linked to useful verification are actually outweighing the prices of chip layout. to deal with those demanding situations engineers are more and more counting on new layout and verification methodologies and languages.  Transaction-based layout and verification, restricted random stimulus iteration, useful insurance research, and assertion-based verification are all ideas that complex layout and verification groups repeatedly use at the present time. Engineers also are more and more turning to layout and verification types in response to C/C++ and SystemC to be able to construct extra summary, better functionality and software program versions and to flee the constraints of RTL HDLs. This new booklet, complicated Verification Techniques, provides particular counsel for those complex verification thoughts. The booklet comprises real looking examples and indicates how SystemC and SCV might be utilized to various complex layout and verification tasks."
                                                                                     - Stuart Swan

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Ingroup checker Notice that each of these lines has three backslashes. Use three /// for doxygen to recognize the comments. Line 1 is taken as brief description of the class. Lines 2,3, are left blank to distinguish brief description from detailed description. Lines 4,5,6,7 are detailed description of the class. Line 9 is in case it is needed to group this in the group called “checker”. It is a good idea to group different tasks and classes for clarification. h> file as follows: 1. /// \defgroup checker checker parts.

Should be able to define expressions that perform arithmetic or logical operations. Good to have schematic tracer option to show HDL design as schematic diagram and help to trace signal through the design. Should be able to watch values of signals as they are changing in simulation. Should be able to trace back the selected signal to source code where it is defined. Allows to store database in compressed form. Allows limit on the waveform size. Following are some of the waveform tools available that have above features: Debussy: FromNovas - Waveform viewing and analysis tool for fast tracing of design structure.

It is expensive too. It is reliably faster and supports almost all the operating systems. It uses central database and have support for many platforms. VSS: is from microsoft and works in windows only. It is not known to be very reliable and data can get corrupted. It comes with repair tool, if something is buggy, repair tool can be used. There is no insight into the code - it is like black box. 34 Advanced Verification Techniques CVS is most common and widely used open source software. It is free and reliable.

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