By R. Joobbani
Routing of VLSI chips is a crucial, time eating, and hard challenge. the trouble of the matter is attributed to the big variety of usually conflicting components that have an effect on the routing caliber. conventional ideas have approached routing through ignoring a few of these elements and implementing pointless constraints as a way to make routing tractable. as well as the imposition of those regulations, which simplify the issues to some extent yet while lessen the routing caliber, conventional techniques use brute strength. they generally rework the matter into mathematical or graph difficulties and fully forget about the explicit wisdom in regards to the routing activity that could tremendously aid the answer. This thesis overcomes the various above difficulties and offers a process that plays routing with regards to what human designers do. In different phrases it seriously capitalizes at the wisdom of human services during this region, it doesn't impose pointless constraints, it considers all of the various factors that have an effect on the routing caliber, and most significantly it permits consistent person interplay through the routing method. to accomplish the above, this thesis provides history approximately a few consultant options for routing and summarizes their features. It then reports intimately the various components (such as minimal quarter, variety of vias, cord size, etc.) that have an effect on the routing caliber, and the several standards (such as vertical/horizontal constraint graph, merging, minimum rectilinear Steiner tree, etc.) that may be used to optimize those factors.
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Additional info for An Artificial Intelligence Approach to VLSI Routing
Domain specific applications: These systems cover a wide variety of applications ranging from diagnostics to design to education, including: Dendral [Buchanan 78], MYCIN [Buchanan 84], Rl [McDermott 80], TALIB [Kim 84], DAA [Kowalski 84], VlSI deSign [Mitchell 84], SOPHIE [Brown 82], Thevenin tutor [Joobbani 85a, Joobbani 85b], and the LISP tutor [Anderson 84]. The rest of this chapter describes the architecture of rule based systems in general and OPS5 specifically and focuses on the applicability of knowledge· based expert systems to the task of detailed routing of VlSI chips.
Especially, as the name "GREEDY" implies [Aho 74], it searches for local optimums, consequently creating situations where decisions made early make the channel unroutable or increase the width of the channel more than necessary. Also, a cycle in the vertical constraint graph might make the channel impossible to route in the available channel length. Figure 2·11 is an example where the channel cannot be routed in the available channel length. Figure 2·11 (a) shows the initial channel (no net has a pin on the left or right of the channel).
Here the tree Tab (i) and its cost are determined as in case 1(b). Moreover Ta(i) = Tb(i) = Tab(i). 31 4. Ta b is the desired MRST for A if a and b both belong to A, Ta or Tb is the desired n n MRST for A if only an or b n belongs to A respectively. Figure 3·9 shows an example of a channel, a net with 11 pins and the distance between consecutive pins. Table 3·3 shows the step by step calculation of the optimal RST of the channel of Figure 3·9. The desired MRST is shown in Figure 3·10. Aho, et. al.